1. Field of the Invention
The present invention relates to a stacked semiconductor chip package, and more particularly to a stacked semiconductor device and a semiconductor chippackage for adopting the same, wherein either a lead on chip method (hereinafter referred to as "LOC") that bonds leads onto semiconductor chips is employed to alternately arrange the leads of a lead frame to partially coincide with each other on the upper or lower portions of semiconductor chips, or a tape automated bonding ("TAB") method that uses thin metal leads formed on insulating tapes is employed, thereby densely mounting at least two semiconductor chips.
2. Background of the Prior Art
Generally, semiconductor chips of integrated circuits (ICs) or large scale integration (LSI) circuits are mounted on a metal lead frame, and encapsulated with a resin to be mounted on a printed circuit board (PCB). A manufacturing process of a typical resin-encapsulated package will be described below.
A semiconductor chip is mounted on a rectangular die pad punched into a metal lead frame by a predetermined interval via a predetermined method, e.g., a thermo-compression method by means of an adhesive such as Silver (Ag) or epoxy. One end of leads formed along the die pad are wire bonded to be connected to electrode pads of the semiconductor chips. Here, the die pad is supported by at least one tie bar. A package body is formed to wrap the semiconductor chip and wire for providing environmental protection by means of a molding member, e.g., an epoxy molding compound (hereinafter referred to as "EMC") via a common molding process.
In connection with the general resin-encapsulated semiconductor package, high density mounting within a smaller PCB area can be realized by forming thin and minimized packages as being strived for and advanced. However, the mounting density cannot be improved over a certain level. Therefore, a chip on board method (hereinafter referred to as "COB") for directly mounting the semiconductor chips on the PCB, a stacked package method for stacking the semiconductor chips or semiconductor packages, etc., are being studied.
Especially, a method associated with a semiconductor memory chip allows leads, that is, 16n bare I/0 pins, to be connected in parallel for increasing memory capacity. For this purpose, at least two leads of the same package are stacked, or two semiconductor chips are stacked to be encapsulated by a resin as one package body, and the like.
FIGS. 1A and 1B shows one example of a semiconductor package by a conventional method, wherein FIG. 1A is a plan view of the semiconductor package, and FIG. 1B is a cross-sectional view of the semiconductor package shown in FIG. 1A.
Referring to FIGS. 1A and 1B, semiconductor package 10 is a single-type package. A semiconductor chip 2 is mounted onto the upper portion of a die pad 1 while interposing an insulating adhesive 5 therebetween. Bonding pads (not shown) of the semiconductor chip 2 are bonded to inner leads of leads 3 by means of wires 4, and an EMC is used to mold the resultant structure to form a package body 6.
The above described semiconductor package 10 has a surface mounting package structure of dual-in line package (DIP)-type or a quad-flat package (QFP)-type, in which an outer lead externally projecting from the package body 6 is provided in the mounting direction, a mounting connection portion is attached on the upper portion of a lead frame by means of an adhesive, and respective inner leads electrically corresponding to respective semiconductor chip pads are connected by means of metal wires, thereby completing the semiconductor package 10 through the molding with the EMC.
However, the above-described semiconductor package is suitable for mounting a small scale semiconductor chip, but cannot be applied to mounting a large scale semiconductor chip.
FIGS. 2A and 2B illustrate another example of a conventional semiconductor package, wherein FIG. 2A is a plan view showing the semiconductor package, and FIG. 2B is a cross-sectional view showing the semiconductor package illustrated in FIG. 2A.
Referring to FIGS. 2A and 2B, the semiconductor package 20 has a semiconductor chip 12 directly mounted onto a plurality of leads 13 through the LOC method. Here, the semiconductor chip 12 is attached to the plurality of leads 13 by interposing insulating adhesive tapes 11, and a bonding pad portion (not shown) of the semiconductor chip 12 is connected to the leads 13 by means of metal wires 14. Finally, the package body 16 is formed by the molding with the EMC.
The semiconductor package 20 is advantageous in that the semiconductor chip is directly mounted to the inner leads without using the die pad, thereby increasing the mounting efficiency of the semiconductor chip. However, as explained with reference to FIG. 1, it is difficult to increase the efficiency of the PCB mounting when mounting the semiconductors package on the PCB.